High accuracy, high impedance differential to single-ended current converter

ABSTRACT

A correction circuit is provided to improve current accuracy by sensing the error current of a first variable current source and substracting it from the output of a second variable current source. It also increases output impedence by sensing incremental output current and cancelling its effect.

BACKGROUND AND SUMMARY OF THE INVENTION

The present invention relates generally to current sources and more specifically to high impedance differential to single-ended current converters.

Ideal current sources have output impedance of infinity and provide a specific current level. In actuality, these characteristics can only be approximated. In all implementations of current sources, they deviate from the ideal in at least two ways. The first is a parasitic parallel resistance which lowers the current source impedance from its ideal value of infinity. A second deviation is in the current level itself from the desired value because of current errors and biasing errors. This is particularly bothersome in bipolar current sources. Since the collector impedance of a bipolar transistor is inversely proportional to the current level, it is difficult to design a high impedance current source for high current levels with bipolar transistors. Also, it is difficult to set a precise current level since base current errors accumulate in bipolar transistors and drift as the bipolar transistor parameters drift with temperature changes.

A typical bipolar current source or current stack is illustrated in FIG. 1 including transistors Q1 and Q2 having their emitter-to-collector current paths connected between nodes N3 and N4. Their bases are connected to nodes N1 and N2. Nodes N1, N2 and N4 are DC bias levels with the output current I-OUT being being at node 3 and being represented by equation (1).

    I.sub.out =ICQ2=IEQ1-IBQ1-IBQ2                             (1)

The desired value for an ideal current source is IEQ1. The base currents for transistors Q1 and Q2, namely IBQ1 and IBQ2, represent error terms.

The output impedance is dominated by the collector-base impedance of Q2, which is given by equation (2),

    R=1/hobQ2                                                  (2)

as the inverse of the small signal grounded base output admittance hobQ2. hob is a linear function of collector current level, so as the magnitude of the current source increases, its impedance decreases and deviates further from the ideal.

The prior art generally includes a sensor which provides a feedback to the input to cancel input bias and noise currents. A typical example in a differential bipolar amplifier is U.S. Pat. No. 4,639,684 to Laude. In operational amplifiers, the output impedance of a voltage gain stage has been increased by feeding back current from the output current stage as shown in U.S. Pat. No. 4,560,948 to Prentice and Cotreau.

Thus, it is an object of the present invention to reduce the current error produced by the base currents of the transistors Q1 and Q2 as well as minimizing the reduction of output impedance due to the collector impedance of the output transistor, and to make these improvements independent of the magnitude of the current source.

Another object of the present invention is to provide a high impedance differential to single-ended current converter or transconductance stage.

These and other objects of the invention are attained by providing a correction circuit connected between the subtracting means for subtracting the output current of a first output terminal of a first variable current source from the current at a second or output terminal of a second variable current source a differential current to single ended current converter. The correction circuit senses the incremented current through output transistors at the second output, which forms the converter output, and provides the sensed incremented current to the output to cancel the effect of the incremented current through the output transistors on the impedance of the converter's output terminal. This cancellation of incremented current maintains the output impedance at substantially infinity without substituting a parallel impedance circuit.

The output circuitry includes a first transistor having its conduction path connected in series between a first reference terminal and the converter output terminal and a second transistor having its conduction path connected between the subtracting circuit and the converter output terminal. The correction circuit is connected to the control terminals of the first and second transistors and the conduction path of the second transistor to monitor the current at the control terminals of the first and second transistor and apply the correcting current to the conduction path of the second transistor.

The correction circuit includes a third transistor having its conduction path connected between the control terminals of the first and second transistor and a fourth transistor having its conduction path connected between the second transistor's control terminal and a portion of the conduction path of the second transistor where it is connected to the subtracting circuit. The first, third and fourth transistors are of the same conductivity type and the second transistor is of a different conductivity type. Wherein the transistors are bipolar transistors, the third and fourth transistors have alpha's of approximately 1. The subtracting circuit includes a current mirror.

A high output impedance current stage may also be formed using the previously described circuitry wherein the first and second transistors form an output stage connecting a first and second current source and a current input. The correction circuit provides appropriate compensation and maintains a high output impedance as previously described.

Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic of a current source of the prior art.

FIG. 2 is a schematic of a high impedance, high accuracy current source according to the principles of the present invention.

FIG. 3 is a schematic of a high impedance, high accuracy current mirror according to the principles of the present invention.

FIG. 4 is a schematic of a high impedance, high accuracy differential to single-ended current converter according to the principles of the present invention.

FIG. 5 is a schematic of another embodiment of a differential to single-ended current converter or high accuracy transconductance stage according to the principles of the present invention.

FIG. 6 is a schematic of a current converter having a high output impedance stage according to the principles of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 2 shows a high impedance, high accuracy current source 20 including a first current source including transistors Q1 and Q2 having their emitter-collector current path connected in series between a reference node N4 and an output node N3. A correction circuit connected between the bases of Q1 and Q2 and the output node N3 includes transistors Q3 and Q4. The transistors Q3 and Q4 form a second current source in parallel with the first, and the parallel combination has smaller error currents and higher impedance than the first current source alone. The emitter-collector path of Q3 is connected between the bases of transistors Q1 and Q2 and has its base connected to a reference node N1. The transistor Q4 has its emitter-collector path connected between the base of transistor Q2 and the output node N3 and has its base connected to a reference node N2. DC biasing levels are connected to nodes N1, N2 and N4 as in FIG. 2. Base current errors of first current source transistors Q1 and Q2 flow through second current source transistors Q3 and Q4 and are added to the output terminal N3.

The second current source formed by transistors Q3 and Q4 operates at a lower current than the primary current source Q1 and Q2, and the base error currents of Q3 and Q4 can be set to be small and independent of the primary current source Q1 and Q2. Since the second current source operates at lower current, it has a higher output impedance than Q2. The second current source formed by transistors Q3 and Q4 also provides a higher output impedance to the output terminal by cancelling the impedance contribution of the first current source formed by transistors Q1 and Q2. The correction circuit formed by transistors Q3 and Q4 also add current to the output terminal at node N3 as a function of the base current of the transistors Q1 and Q2 and add impedance to the output terminal of node N3 while canceling the lower output impedance of Q2.

The resistor R1 connects the reference node N4 to the emitter-collector path of transistors Q3 and Q4 to supply a very small DC bias current. This is not necessary and may be deleted.

To analyze the correction of the base current according to the circuit of FIG. 2, reference should be made to the following equations wherein A is the alpha of the transistor and ICQ2 is defined by equation (1). ##EQU1## The alpha's of transistors 3 and 4 are selected to be approximately equal to one and are generally in the range of 0.99 to 0.999. This will cause the terms represented by the base current error of transistors Q1 and Q2 to be reduced by one or two orders of magnitude, as illustrated in equation (5) compared to the prior art of equation (1).

To analyze the impedance of the circuit in FIG. 2, both transistors Q2 and Q4 have a collector-base impedance due to transistor hob. As the collector of Q2 moves by a voltage V, a current of V*hobQ2 flows towards the base. Since the collector impedance of Q3 is very high compared to the emitter impedance of Q4, the current V*hobQ2 flows into the emitter of Q4 and on to the collector where it is summed with the original current to which it is opposite and almost equal. The net current due to Q2 is:

    I=V*hobQ2*(1-A4)                                           (6)

A current due to hobQ4 also flows from the node N3 to the base of Q4 which is AC grounded. Total current flow due to a voltage excursion V at node N3 is:

    I=V*(hobQ4+hobQ2(1-A4))                                    (7)

and the effective impedance is:

    R=1/(hobQ4+hobQ2(1-A4))                                    (8)

With A4 selected to be substantially equal to one, the contribution of the admittance of Q2 is substantially reduced by orders of magnitude. Since the signal base output admittance is approximately equal to I_(c) /BV_(A), where B is transistor grounded emitter current gain and V_(A) is transistor early voltage, both constant for similar transistors, hob is proportional to I_(c). Thus, the admittance of Q4 is one if not two orders of magnitude smaller than the contribution of the admittance of Q2. Thus, the total admittance of the circuit of FIG. 1 versus the circuit of FIG. 2 are many orders of magnitude smaller when one compares equations (2) and (8). Since the admittance is the inverse of the output resistance, the output resistance of FIG. 2 and equation (8) are orders of magnitude larger than that of FIG. 1 and equation (2).

Ideally, current mirrors require an exact image of the current between the input and output with an infinite output impedance and no errors. Another function of the current mirror can be referred to as a current pulley wherein the input current is reversed on the output so as to convert a current source at the input terminal to a current sink at the output terminal and vice versa. The high impedance, high accuracy current source 20 of FIG. 2 is provided in a high impedance, high accuracy current mirror 30 of FIG. 3.

The current mirror 30 includes an input leg 34 receiving an input current I-IN and an output leg 32 connected thereto providing an output current I-OUT. The output leg 32 includes a high impedance, high accuracy current source of FIG. 2 including transistors Q1, Q2, Q3 and Q4. Reference to the description of the operation of correction of this high impedance, high accuracy current source should be made. The input leg 34 of the current mirror 30 includes a transistor Q11 having its emitter-collector path connected between reference node N4 and the input node N5 and a transistor Q13 having its emitter-collector path connected between the base of transistor Q11 and the input node N5. The base of transistor Q13 is connected to the base of transistor Q3 at node N1 which is also connected to the emitter-collector path of Q11. A diode D12 connects node N1 to node N5. The base Q4 of the output current leg 32 at node N2 is also connected to node N5. The node N2 may be connected to any reference source and need not be connected at N5. The diode D12 is only one convenient way to provide a reference voltage for node N2.

The transistors Q11 and Q13 are connected and operate as Q1 and Q3 respectively, such that the sum of the currents in the collectors of Q11 and Q13 is equal to the sum of the currents in the collectors of Q1 and Q3.

In operation, the input I-IN of current mirror 30 pulls node N5 and node N1 down until Q11 and Q13 are turned on and I-IN=ICQ11+ICQ13. At this point, the voltage at node N1 is exactly the value necessary to sustain the current of ICQ11+ICQ13=I-IN. This voltage at node N1 is also applied to the base of Q3. Device Q3 matches Q13, Q1 matches Q11, so that the voltage node at N1 is exactly that necessary to provide ICQ3+ICQ1=I-IN. The accurate mirroring of the input current I-IN to the output current I-OUT is evident from the following equations (9)-(12):

    I.sub.in =ICQ11+ICQ13=ICQ1+ICQ3                            (9)

    ICQ2=ICQ1-IBQ2                                             (10)

    ICQ4-(ICQ3+IBQ3)A4                                         (11)

    I.sub.out =ICQ2+ICQ4=ICQ1+ICQ3*A4-IBQ2(1-A4)               (12)

As in the previous embodiments, A4 is substantially equal to 1 and therefore, the error due to the base current IBQ2 is substantially reduced by orders of magnitude and the equation (12) for I-OUT becomes substantially the same as the current I-IN of equation (9). The analysis of the output impedance because of the relationship between Q2 and Q4 of equations (8) still apply to the output node N3 of the current mirror 30. By ratioing emitter areas of Q3 and Q13, and Q1 and Q11, the accurate mirrored current can be an accurate multiple of the input current.

A differential to single-ended current converter 40 is illustrated in FIG. 4. Such converters provide variable gain in operational amplifiers and ideally produce zero output current for zero input differential current and infinite output impedance. Less than infinite output impedance lowers the voltage gain and power supply rejection rating. Non-zero output current when differential input current is zero affects, for example, the input offset voltage. Thus, the current converter 40 incorporates the high impedance, high accuracy current sources 20 of FIG. 2, since it provides improved output impedance and reduces current errors.

The current converter 40 includes a first variable current source 44 having an input node N16 to receive input current I-IN1 and a second variable current source 42 having an input node N6 to receive a second input current I-IN2. The output of the first variable current source 44 at node N13 is subtracted from the output of the second variable current source 42 at node N3. This difference is the output current I-OUT at node N3. A current mirror or pulley 46 interconnects node N13 and node N3 to subtract the output current of the first current source 44 from the second current source 42 at node N3. The current mirror 46 would be the high impedance, high accuracy current mirror 30 of FIG. 3. Since each of the current elements include high impedance and high accuracy, the total differential to single-ended current converter 40 produces a high impedance, high accuracy output.

A modification to the differential to single-ended current converter 40 of FIG. 4 is shown as current converter 40' in FIG. 5. Instead of adding current and impedance to the output node N3 for the second high accuracy current source 42', these corrections are subtracted from the current and impedance of the first high impedance, high accuracy current source 44 without substituting a higher impedance of Q4 of the correction circuit. This is done at the output of the current mirror 46. This modification results in even higher or substantially infinite output impedance than that of the high accuracy current source.

In this modification, a transistor Q5 having its collector-emitter path connected between the output node N3 and the output node N17 of the current mirror 46. A transistor Q6 has its emitter-collector path connected between the base of Q5 and node N17. The emitter-collector path of Q4 is disconnected from between the base of Q2 and the output terminal node N3 and is connected between the base of Q2 and the base of Q5. Thus, the base currents of Q1 and Q2 flow through Q6 to node N17. Transistor Q2 along with Q5 forms the high impedance output node at N3 and Q6 provides a conduit for the error currents to the output node. The base currents of Q1, Q2 and Q5 are cancelled by flowing through Q6 to the output node N17 of the current mirror where they are subtracted from the current mirror output current resulting from error currents through parasitic impedance.

This method also cancels the reduction of output impedance of Q1, Q2 and Q5, but does not include substituting the impedance of Q4 or Q6. Instead, the error currents are sensed at the base of Q1, Q2 and Q5 and are fed back as cancelling current to the output. Thus, the output impedance is substantially infinite.

The collector current of Q5 is reduced by exactly the same error current by which Q2 collector current is reduced. For no input, the two variable current sources 42 and 42' provide exactly matched currents through Q2 and Q5 producing no output current.

Using equations (1), (3) and the following equations, (13)-(15), the output current I-OUT is defined in equation (16) as follows: ##EQU2##

With no input current on nodes N6 and N16 and using the matching high accuracy current sources 44 and 42', and the emitter currents of transistors Q1 and Q11 are equal and are also equal to the current mirror current IM so IEQ1=IEQ11=IM, and thus, the error current for zero differential input current is defined as follows: ##EQU3##

Since the alpha's are very close to one, each error term is orders of magnitude smaller than what it would have been if uncorrected. In a standard implementation, the base currents appear whole and the output error current is

    I.sub.outER =IBQ1+IBQ2-IBQ5                                (18)

orders of magnitude larger. Further, the situation is even better than this since the error current of equation (17) is matched by a similar error due to the high impedance, high accuracy current source of Q11, Q12, Q13 and Q14 which drive the current mirror 46. The output error current is actually the difference between the small error current of equation (17) and the matching error current of the Q11, Q12, Q13, Q14 current source. This is not presented here since it does not assist in understanding the invention.

The current converter of FIG. 5 also increases output impedance by routing error currents from parasitic impedances through the same path above to cancel themselves. If output nod N3 moves by a voltage V, a current flows through hobQ2 and hobQ5. The current through Q2 flows into Q4's emitter, on into Q6's emitter, and on into Q5's emitter, and into node N3 where it is opposite and equal to the original current, cancelling itself.

Likewise, the current through hobQ5 flows into Q6's emitter, into Q5's emitter, to node N3 where it is also equal and opposite to the original hobQ5 current, also cancelling itself.

These cancellations of error currents are produced without substituting a parallel high output impedance device as in the other embodiments. ##EQU4##

Net current out of node N3: ##EQU5##

Since the alpha's are very close to one, the net output current is orders of magnitude smaller than for a standard converter and, hence, the output impedance level is orders of magnitude higher.

Although the differential to single-ended current converter 40 of FIG. 5 has been described in a high accuracy, high impedance circuit, it can also be used as a high impedance circuit alone. The high accuracy results from using the principles of the circuit of FIG. 2 in the input and output current sources 44 and 42, and the high accuracy current mirror of FIG. 3. The high output impedance results from the interrelationship of transistors Q2, Q4, Q5 and Q6 in cancelling the current induced impedance errors without substituting a higher impedance source. The principles of the high output impedance circuit of transistors Q2, Q4, Q5 and Q6 can be used independent of the high accuracy produced by input current source 44 and current mirror 46. If high accuracy is not needed, any input current source and current mirror may be used and the substantially infinite output impedance would be maintained by Q2, Q4, Q5 and Q6.

Some implementations of the prior art, to improve impedance levels, have cancelled hob current with current from hob of a matching transistor. This works fairly well but does depend on transistor matching characteristics and is good for perhaps 10X or one order of magnitude improvement at most. This invention does not depend on a transistor match and offers considerably more improvement. For transistor beta as low as 100, 50X improvement is possible.

The substantially high output impedance stage is illustrated in FIG. 5 may also be used to provide a high output impedance for any current converter. As illustrated in FIG. 6, the current converter 40" includes a differential voltage input to current output stage 47. It includes a pair of input transistors Q15 and Q16 having their bases connected to input terminals N20 and N21 respectively, and their emitter-collector path connected to a common current source 48. The other end of the emitter-collector path of Q15 is connected to node N6 of the output stage and the other end of the emitter-collector path of Q16 is connected to node N23.

If the inputs at nodes N20 and N21 are equal and the size of Q15 and Q16 are equal, half the current from current source 48 appears at each of the nodes N6 and N23. As the difference between the voltage input on nodes N20 and N21 change, so does the output current at nodes N6 and N23. The output stage includes the current source 42' of FIG. 5. Another way of viewing the current source 42' is a transistor Q1 and resistor R1 forming a first fixed current source connected between node N4 and the current input terminal N6. The remainder of the circuit Q2 and Q5 form an output stage which interconnects the input at node N6, the first current source 42' including transistor Q1 and a second current source 44' which is connected at node N17 to the output N3. The circuit Q2 and Q5 Provide at the output N3 a current which is the sum of the current coming from the first current source 42', the input at node N6 and the current from current source 44'. Transistors Q3, Q4 and Q6 provide the appropriate correction to provide the substantially infinite output impedance as previously described.

The current source 42' and 44' are selected such that when they are equal inputs at N20 and N21, the current drawn from terminal N6 plus the current drawn by current source or sink 44' sums to equal the current sourced by current source 42'. Thus, the output current I-OUT at output node N3 is zero. This is the DC condition. As the current I-IN2 at node N6 becomes less, more current from constant current source 42' is available and therefore, provides an I-OUT which drives the load on terminal N3. If the current I-IN2 at node N6 is greater than the DC or steady-state level, it draws current from the output node N3 and therefore, sources current from the load attached to node N3.

Thus, it can be seen that the substantially infinite output impedance provided by Q2, Q5, Q4, Q6 can be used in other circuits than that described for FIG. 5. This circuit may be used to provide a high output impedance for output current stage wherein the input may be a single current.

Although the present invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only, and is not to be taken by way of limitation. All the transistors except Q5 have been illustrated as PNP's, but the principle is also applicable to NPN transistors in which case Q5 would be a PNP. Also, the present invention could be used with field effect transistors. The spirit and scope of the present invention are to be limited only by the terms of the appended claims. 

What is claimed:
 1. A differential current to single-ended current converter including first and second variable current sources having first and second current input terminals and first and second output terminals, respectively, and subtracting means for subtracting output current at said first output terminal from the current at said second output terminal, said second output terminal being said converter's output terminal;wherein said second variable current source includes a first transistor having its emitter-collector path connected in series between a first reference terminal and said converter's output terminal, and includes a second transistor having its emitter-collector path connected between said subtracting means and said converter's output terminal; and including correction means connected to bases of said first and second transistors and the emitter-collector path of said second transistor for sensing incremental current through said first and second transistors and providing said sensed incremental current to said emitter-collector path of said second transistor to cancel the effect of the incremental current through said first and second transistors on the impedance at said converter's output terminal.
 2. A current converter according to claim 1, wherein said correction means includes a third transistor having its emitter-collector path connected between said bases of said first and second transistors and a fourth transistor having its emitter-collector path connected between said second transistor's base and the portion of said second transistor's emitter-collector path connected to said subtracting means.
 3. A current converter according to claim 2, wherein said third and fourth bipolar transistors have alpha's of approximately one.
 4. A current converter according to claim 2, wherein said first, third and fourth transistors are of a first conductivity type and said second transistor is of a secondary conductivity type.
 5. A current converter according to claim 1, wherein said subtracting means includes a current mirror having input and output legs connected to said first output terminal and said second transistor's emitter-collector path respectively, for providing a difference signal at said converter's output terminal.
 6. A differential current to single-ended current converter including first and second variable current sources having first and second current input terminals and first and second output terminals, respectively, and subtracting means for subtracting output current at said first output terminal from the current at said second output terminal, said second output terminal being said converter's output terminal:wherein said second variable current source includes first, second, third and fourth transistors each having a control terminal and a series current path between a first and second terminal; said first transistor having its first and second terminals connected in series between a first reference terminal and said converter's output terminal; said second transistor having its control terminal connected to a second reference terminal and its first and second terminals connected between said control terminals of said first and third transistors; said third transistor having its first terminal connected to said converter's output terminal and its second terminal connected to said subtracting means; said fourth transistor having its control terminal connected to a third reference terminal and its first and second terminals connected between said third transistor's control terminal and said third transistor's second terminal.
 7. A current converter according to claim 6, wherein said transistors are bipolar transistors, and said control, first and second terminals are base, collector and emitter terminals, respectively.
 8. A current converter according to claim 7, wherein said second and fourth transistors have alpha's of approximately one.
 9. A current converter according to claim 6, wherein said subtracting means includes a current mirror having input and output legs connected to said first output terminal and said third transistor's second terminal respectively for providing a difference signal at said third transistor's first terminal.
 10. A current converter according to claim 6, wherein said first, second and fourth transistors are of a first conductivity type and said third transistor is of a second conductivity type.
 11. A high output impedance current circuit including input and output ports, first and second current sources having first and second current output terminals, respectively, and output means for providing an output current at said output port which is the sum of currents at said input port and said first and second output terminals, said output means comprising:a first transistor having its emitter-collector path connected in series between a first output terminal and said output port, and said input port is connected to said emitter-collector path of said first transistor; and a second transistor having its emitter-collector path connected between said second output terminal and said output port; and correction means connected to bases of said first and second transistors and the emitter-collector path of said second transistor for sensing incremental current through said first and second transistors and providing said sensed incremental current to said emitter-collector path of said second transistor to cancel the effect of the incremental current through said first and second transistors on the impedance of said output port.
 12. A current circuit according to claim 11, wherein said correction means includes a third transistor having its emitter-collector path connected between said bases of said first and second transistors and a fourth transistor having its emitter-collector path connected between said second transistor's base and said second output terminal.
 13. A current circuit according to claim 12, wherein said third and fourth bipolar transistors have alpha's of approximately one.
 14. A current circuit according to claim 12, wherein said first, third and fourth transistors are of a first conductivity type and said second transistor is of a secondary conductivity type.
 15. A high output impedance current circuit including input and output ports, first and second current sources having first and second current output terminals, respectively, and output means for providing an output current at said output port which is the sum of currents at said input port and said first and second output terminals, said output means comprising:first, second, third and fourth transistors each having a control terminal and a series current path between a first and second terminal; said first transistor having its first terminal connected to said first output terminal and said input port and its second terminal connected to said output port; said second transistor having its control terminal connected to a first reference terminal and its first and second terminals connected between said control terminals of said first and third transistors; said third transistor having its first terminal connected to said output port and its second terminal connected to said second output terminal; said fourth transistor having its control terminal connected to a second reference terminal and its first and second terminals connected to said third transistor's control terminal and said third transistor's second terminal, respectively.
 16. A current circuit according to claim 15, wherein said transistors are bipolar transistors, and said control terminal is a base terminal and first and second terminals are collector and emitter terminals.
 17. A current circuit according to claim 16, wherein said second and fourth transistors have alpha's of approximately one.
 18. A current circuit according to claim 15, wherein said first, second and fourth transistors are of a first conductivity type and said third transistor is of a second conductivity type.
 19. A differential current to single-ended current converter including first and second variable current sources having first and second current input terminals and first and second output terminals, respectively, and subtracting means for subtracting output current at said first output terminal from the current at said second output terminal;wherein said first variable current source included a first and second transistor having their emitter-collector paths connected in series between a first reference terminal and said first output terminal, and a first correction means connected to bases of said first and second transistors and said first output terminal for adding current to said first output terminal as a function of base current of said first and second transistors and adding incremental current to said first output terminal to increase impedance level of said first output terminal as a function of current at said first output terminal; and wherein said second variable current source includes third and fourth transistors having their emitter-collector paths connected in series between said first reference terminal and said second output terminal, and a second correction means connected to bases of said third and fourth transistors and said second output terminal for subtracting current from said first output terminal as a function of base current of said third and fourth transistors and adding incremental current to said second output terminal to increase impedance level at said second output terminal.
 20. A current converter according to claim 19, wherein said first correction means includes a fifth transistor having its emitter-collector path connected between said bases of first and second transistors and a sixth transistor having its emitter-collector path connected between said second transistor's base and said first output terminal. 